1. Field of the Invention
This invention relates to a read out circuit for a detector array, and more particularly to an address mapped repartitioned digital pixel.
2. Description of the Related Art
A focal plane array (FPA) includes a two-dimensional detector array of detector elements, or pixels, typically organized by columns and rows and a read out integrated circuit (ROIC). The detector array and ROIC may be integrated into a single layer in which each cell includes a detector element and a readout circuit or may be separate layers in which each detector element is electrically coupled to a corresponding readout circuit.
It is common for the readout circuit within the pixel to be able to accumulate charge from a photo-diode, corresponding to the total flux of light of various wavelengths. Often, the charge is accumulated on a capacitive element that effectively integrates charge, producing a voltage, the voltage corresponding to the intensity of the flux over a given time interval called an integration interval. The photo-diode may be coupled to the capacitive element via a MOS transistor or direct injection gate that is biased with a voltage. A circuit element comprises circuitry capable of resetting the voltage of capacitive element back to an initial condition and circuitry capable of conveying a charge or voltage to a column (or row) wire for transfer to an output of array. This ROIC configuration is referred to here as an “analog pixel”. Such a voltage or charge can be digitized by circuitry associated with the focal plane array resulting in binary values, at least one value for each pixel of the focal plane array. Thus, a focal plane array can be used to convert a two-dimensional pattern of flux into a two-dimensional array of binary values, such resulting array often called a digital image.
One variant of the analog pixel, sometime called “sub-frame accumulation” uses two integration capacitors in each pixel to extend the effective well capacity. Charge is initially accumulated onto a 1st capacitor in each pixel and then, at some sub-frame rate, the signal is averaged with the secondary capacitor, then the primary capacitor is reset before continuing its accumulation. This has the effect of increasing the effective charge well capacity for better SNR. US 2012/0006971 discloses another variant in which the secondary capacitor in each pixel is replaced with analog storage in a separate CMOS device so that the averaging may be done in a radiation-hardened manner.
An Orthogonal Transfer FPA allows each pixel's charge to be shifted both vertically and horizontally on the array (Burke et al., “The Orthogonal-Transfer Array: A New CCD Architecture for Astronomy, Proc. SPIE 5499, Optical and Infrared Detectors for Astronomy, 185, Sep. 29, 2004). The ROIC includes additional transfer capacitors and control voltages to shift the pixel charge. An Orthogonal Transfer FPA enables “on-chip” frame summing, in which sub-frames are registered in response to a motion signal representative of the motion of the scene with respect to the FPA, so that summed-values from the same point in the scene are shifted between sub-frames to remain associated with the pixel where that point in the scene is currently imaged, and thus to reduce smearing within a frame. In the TDI operating mode of US 2012/0006971, the values in the CMOS layer are similarly shifted from each sub-frame to the next to provide image stabilization.
The effective amount of charge, (i.e., signal), that is accumulated by an analog pixel over an integration interval can be increased by the addition of a digital counter circuit thereby forming a “digital pixel”. In some examples, each digital pixel is given a unique digital counter circuit. Additional circuitry can be added to the digital pixel to allow a predetermined amount of charge to be removed from the capacitive element of the pixel and correspondingly to increase the value of the digital counter by one count. Thus, over the lapsed period of time of an integration interval, the capacitive element of the pixel can integrate photo charge, a circuit within the pixel can remove predetermined quantities of charge, and a digital counter can count the number of charge removals, and thereby accumulate the applied signal. In this manner, the effective amount of signal that is accumulated by the digital pixel over an integration interval can be increased relative to an analog pixel because the digital counter extends the integration range of the capacitive element. The type of digital counter used can be of any logical variation, including binary, gray code, Linear-Feedback-Shift-Register (LFSR), or any other digital count circuit that can count charge removals. Furthermore, the relative sign of the signal accumulation may be plus or minus, relative to the charge, so that signal accumulation could be viewed as a charge addition in some cases and charge subtraction in others, possibly with the sign changing over time.
A class of pixel circuits called “digital pixels” also known as “in-pixel ADCs” are illustrated in FIG. 1. A focal plane array 100 includes a two-dimensional detector array 195 of detector elements, or pixels 190, organized by columns and rows, and a ROIC 102. It is common for a circuit within the pixel 190 to be able to accumulate charge from a photo-diode 105, corresponding to the flux 110 of light of various wavelengths. A common digital pixel circuit features a capacitive element 115 for integrating photo charge to produce a voltage, a MOS transistor or direct injection gate 120 biased with a voltage Vbias that couples photo-diode 105 to capacitive element 115, a comparator 125 which detects when the voltage exceeds a reference voltage Vref, a charge removal circuit 135 which removes a predetermined fixed amount of charge from the capacitive element 115, and a digital counter circuit 145 which increments each time an amount of charge is removed from the capacitive element. Reset logic 140 supplies a clock-type signal to the charge removal circuit 135, triggering the charge removal circuit to remove the predetermined amount of charge from the capacitive element 115 responsive to a signal from the comparator 125 indicating that the voltage across the capacitive elements has exceeded the reference voltage. With each charge removal/reset event, the digital counter 145 is incremented. The value of the digital counter 145 may be read out via a tri-state gate 150 on a data-out line 180, as shown in FIG. 1. Multiple other means of conveying the value of digital counter 145 to a set of outputs exist as alternatives to tri-state gate 150, as will be appreciated by those skilled in the art. For example, the values may be shifted out.
If “integrate-while-read” capability is required, then an additional set of digital storage elements or latches also have to be installed within the pixel 190. For example, latches may be connected between the digital counter 145 and tri-state gate 150. In integrate-while-read mode, at the end of an integration interval, the value of the digital counter 145 is copied to the digital storage element, preserving the values for read-out, for example, one row or one column at a time, and freeing up the digital counter 145 to be used for further counting of integrated charge.
In a common digital pixel circuit, the size of the capacitive element is often reduced to a relatively small value (for example, 1.0 femto-farads or 10 femto-farads) and the number of counter bits is some number of bits that results in a large range of count values, for example 16 bits. Correspondingly, the voltage range of the capacitive element 115 is often relatively small, for example 250 millivolts. In this configuration, the digital counter 145 can act as an analog-to-digital converter, resulting in the ability of the circuit of a pixel to perform analog-to-digital conversion and thus be referred to as an “in-pixel ADC” circuit. The predetermined amount of charge can also be called a “quanta” of charge. The charge removal from the capacitive element 115 may be a reset back to a first voltage using a simple device such as a MOSFET. The charge removal may also be a more complex circuit that removes a quantum of charge causing the capacitive element voltage to go from one value to a second value.
As described in Brian Tyrell et al. “Design Approaches for Digitally Dominated Active Pixel Sensors: Leveraging Moore's law Scaling in Focal Plane Readout Design” Quantum Sensing and Nanophotonics Devices V. Proceedings of the SPIE, Vol 6900 2008, in-pixel Orthogonal Transfer Structures can be incorporated into the digital FPA architecture. A multiplexed input is added to the counter/register structure to enable orthogonal transfer of digital data between adjacent pixels. As illustrated in FIG. 2, the digital data or “count” 200 in an FPA 202 moves left or right, up or down from one adjacent pixel 204 to the next. This in-pixel structure results in a large number (size of the array) of simultaneous register transfers that increases complexity and power consumption and produces a large noise spike.